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The Feasibility of a VLSI Chip for Ray Tracing Bicublic Patches
March 1987 (vol. 7 no. 3)
pp. 33-44
Ron Pulleyblank, HP Laboratories
John Kapenga, Western Michigan University
In this article we explore the possibility of a VLSI chip for ray tracing bicubic patches in Bezier form. The purpose of the chip is to calculate the intersection point of a ray with the bicubic patch to a specified level of accuracy, returning parameter values (u,v) specifying the location of the intersection on the patch, and a parameter value, t, which specifies the location of the intersection on the ray. The intersection is calculated by succesively subdividing the patch and computing the intersection of the ray with a bounding box of each subpatch until the bounding volume meets theaccuracy requirement. There are two operating modes: another in which all intersections are found. This algorithm (and the chip) correctly handle the difficult cases of the ray tangentially intersecting a planar patch and intersections of the ray at a silhouette edge of the patch. Estimates indicate that such a chip could be implemented in 2-micron NMOS (N-type metal oxide semiconductor) and could computer patch-ray intersections at the rate of one every 15 microseconds for patces that are prescaled and specified to a 12-bit fixed point for each of the x, y, and z components. A version capable of handling 24-bit patches could compute patch/ray intersections at the rate of one every 140 section point could be performed with the addition of nine scalar subtractions and six scalar multiplies. Images drawn using a software version of the algorithm are presented and discussed.

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Ron Pulleyblank, John Kapenga, "The Feasibility of a VLSI Chip for Ray Tracing Bicublic Patches," IEEE Computer Graphics and Applications, vol. 7, no. 3, pp. 33-44, March 1987, doi:10.1109/MCG.1987.276963
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