Issue No.03 - March (1987 vol.7)
Bob Fredrickson , Hewlett-Packard Co.
Andy Goris , Hewlett-Packard Co.
This article describes an approach to fast image generation that uses a high-speed serial scan converter, a somewhat slower frame buffer, and a pixel cache to match the bandwidth between the two. Cache hit rates are improved by configuring the cache to buffer either 4 × 4 or 16 × 1 tiles of frame memory, depending on the type of operation being performed. For line drawing, the implenmention discribed can process 300,000 30-pixel vectors per second. For shaded polygons, the system can fill 16,000 900-pixel polygons per second. In addition to buffering pixel intensity data, the pixel cache also buffer z (depth) values, improving the performance of the z-buffer hidden-surface algorithm. By utilizing z-value caching, the system can process 5800 900-pixel shaded polygons per second with hidden-surface removed.
Bob Fredrickson, Andy Goris, "A Configurable Pixel Cache for Fast Image Generation", IEEE Computer Graphics and Applications, vol.7, no. 3, pp. 24-32, March 1987, doi:10.1109/MCG.1987.276962