This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Resistive Computation: A Critique
RapidPost
ISSN: 1556-6056
Hamid Mahmoodi, San Francisco State University, San Francisco
Sridevi Lakshmipuram, San Francisco State University, San Francisco
Manish Arora, University of California, San Diego, San Diego
Yashar Asgarieh, University of California, San Diego, San Diego
Houman Homayoun, George Mason University, Arlington
Bill Lin, University of California, San Diego, San Diego
Dean M. Tullsen, University of California at San Diego, La Jolla
Resistive Computation [6] replaces conventional CMOS logic with Magnetic Tunnel Junction (MTJ) based Look-Up Tables (LUTs). It has been proposed for tackling the power wall. Spin Transfer Torque RAM (STTRAM) is an emerging CMOS compatible non-volatile memory technology based on Magnetic Tunnel Junctions as a memory bit [3]. The principal advantage of STTRAM is that it is leakage-resistant, which is an important characteristic beyond the 45nm technology node, where leakage concerns are becoming a limiting factor in microprocessor performance. Although STTRAM is a good candidate for replacing SRAM for on-chip memory, we argue in this article MTJ-based LUTs are unnecessarily expensive in terms of area, power, and performance when implementing fixed combinational logic that does not require the reprogramming ability provided by MTJs.
Index Terms:
C.0.a Emerging technologies,B.2.1 Design Styles,B.6.1.e Memory used as logic,B.7.1.a Advanced technologies,B.9.1 Low-power design
Citation:
Hamid Mahmoodi, Sridevi Lakshmipuram, Manish Arora, Yashar Asgarieh, Houman Homayoun, Bill Lin, Dean M. Tullsen, "Resistive Computation: A Critique," IEEE Computer Architecture Letters, 05 Aug. 2013. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/L-CA.2013.23>
Usage of this product signifies your acceptance of the Terms of Use.