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An FPGA-based In-line Accelerator for Memcached
RapidPost
ISSN: 1556-6056
maysam lavasani, The University of Texas at Austin, Austin
Hari Angepat, The University of Texas at Austin, 78712
Derek Chiou, The University of Texas at Austin, 78712
We present a method for accelerating server applications using a hybrid CPU+FPGA architecture and demonstrate its advantages by accelerating Memcached, a distributed key-value system. The accelerator, implemented on the FPGA fabric, processes request packets directly from the network, avoiding the CPU in most cases. The accelerator is created by profiling the application to determine the most commonly executed trace of basic blocks which are then extracted. Traces are executed speculatively within the FPGA. If the control flow exits the trace prematurely, the side effects of the computation are rolled back and the request packet is passed to the CPU. When compared to the best reported software numbers, the Memcached accelerator is 9.15x more energy efficient for common case requests.
Index Terms:
Field programmable gate arrays,Servers,Acceleration,Computer architecture,Program processors,Engines,Throughput,C.2.4.a Client/server,C.1.3.f Heterogeneous (hybrid) systems
Citation:
maysam lavasani, Hari Angepat, Derek Chiou, "An FPGA-based In-line Accelerator for Memcached," IEEE Computer Architecture Letters, 16 July 2013. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/L-CA.2013.17>
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