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Cache Hierarchy Optimization
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ISSN: 1556-6056
Leonid Yavits, Technion-Israel Institute of Technology, Haifa
Amir Morad, Technion, Haifa
Ran Ginosar, Technion, Haifa
Abstract— Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CMP cache hierarchy and optimally allocating area among hierarchy levels under such constrained resources is developed. The optimization framework is extended by incorporating the impact of data sharing on cache miss rate. An analytical model for cache access time as a function of cache size is proposed and verified using CACTI simulation.
Index Terms:
Delays,Optimization,Resource management,Bandwidth,Analytical models,Integrated circuit modeling,Computational modeling,Resource Allocation Optimization,Chip Multiprocessor,Cache Hierarchy,Analytical Performance Models
Citation:
Leonid Yavits, Amir Morad, Ran Ginosar, "Cache Hierarchy Optimization," IEEE Computer Architecture Letters, 16 July 2013. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/L-CA.2013.18>
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