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Coding Last Level STT-RAM Cache For High Endurance And Low Power
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ISSN: 1556-6056
Sadegh Yazdanshenas, Iran University of Science and Technology, Tehran
Mahsa Ranjbar, Iran University of Science and Technology, Tehran
Mahdi Fazeli, Iran University of Science and Technology, Tehran
Ahmad Patooghy, Iran University of Science and Technology, Tehran
STT-RAM technology has recently emerged as one of the most promising memory technologies. However, it’s major problems, limited write endurance and high write energy, are still preventing it from being used as a drop-in replacement of SRAM cache. In this paper, we propose a coding scheme for STT-RAM last level cache based on the concept of value locality. We reduce switching probability in cache by swapping common patterns with limited weight codes to make writes less often as well as more uniform. We also define ceratin policies for swapping these patterns. Our evaluation shows that bit write variance in memory cells can be reduced by about 20% on average resulting in a more uniform wear out directly enhancing lifetime and improving cell reliability. In addition, writes in cache lines can be reduced by 85.77% times on average resulting in less energy consumption and prolonged lifetime. Our method increases memory hierarchy access time by 0.0825% on average which is negligible. Last level cache energy-delay2 is reduced by 57.64% on average. Our Method also makes way for further coding in cache and main memory due to the nonuniformity caused by the coding.
Index Terms:
B.3 Memory Structures,C Computer Systems Organization,C.1 Processor Architectures,B Hardware
Citation:
Sadegh Yazdanshenas, Mahsa Ranjbar, Mahdi Fazeli, Ahmad Patooghy, "Coding Last Level STT-RAM Cache For High Endurance And Low Power," IEEE Computer Architecture Letters, 06 May 2013. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/L-CA.2013.8>
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