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SMT switch: Software Mechanisms for Power Shifting
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ISSN: 1556-6056
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Priyanka Tembey, Augusto Vega, Alper Buyuktosunoglu, Dilma Da Silva, Pradip Bose, "SMT switch: Software Mechanisms for Power Shifting," IEEE Computer Architecture Letters, vol. 99, no. 2, pp. 1, , 5555.
 
 
BibTex
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@article{ 10.1109/L-CA.2012.26,
author = {Priyanka Tembey and Augusto Vega and Alper Buyuktosunoglu and Dilma Da Silva and Pradip Bose},
title = {SMT switch: Software Mechanisms for Power Shifting},
journal ={IEEE Computer Architecture Letters},
volume = {99},
number = {2},
issn = {1556-6056},
year = {5555},
pages = {1},
doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.26},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - IEEE Computer Architecture Letters
TI - SMT switch: Software Mechanisms for Power Shifting
IS - 2
SN - 1556-6056
SP
EP
EPD - 1
A1 - Priyanka Tembey,
A1 - Augusto Vega,
A1 - Alper Buyuktosunoglu,
A1 - Dilma Da Silva,
A1 - Pradip Bose,
PY - 5555
KW - Scheduling
KW - Hardware
KW - Power Management
KW - Computer Systems Organization
KW - Processor Architectures
KW - Other Architecture Styles
KW - Multithreaded processors
KW - Software/Software Engineering
KW - Operating Systems
KW - Process Management
VL - 99
JA - IEEE Computer Architecture Letters
ER -
 
Priyanka Tembey, Georgia Institute of Technology, Atlanta
Augusto Vega, IBM T.J.Watson Research Center, Yorktown Heights
Alper Buyuktosunoglu, IBM T.J. Watson Research Center, Yorktown Heights
Dilma Da Silva, IBM T.J. Watson Research Center, Yorktown Heights
Pradip Bose, IBM T.J. Watson Research Center, Yorktown Heights
Simultaneous multithreading (SMT) as a processor design to achieve higher levels of system and application throughput is a well-accepted and deployed technique in most desktop and server processors. We study the power implications of varying SMT levels i.e., thread counts per core for various multi-threaded applications on a real SMT multicore platform, and introduce a novel software mechanism of changing SMT level of a core to tune platform power. Power-shifting policies by varying per core SMT levels for performance benefits within a power cap are introduced. Projected power savings (of 15%) for a streaming parallel benchmark can be attained using SMT-level power shifting mechanisms.
Index Terms:
Scheduling,Hardware,Power Management,Computer Systems Organization,Processor Architectures,Other Architecture Styles,Multithreaded processors,Software/Software Engineering,Operating Systems,Process Management
Citation:
Priyanka Tembey, Augusto Vega, Alper Buyuktosunoglu, Dilma Da Silva, Pradip Bose, "SMT switch: Software Mechanisms for Power Shifting," IEEE Computer Architecture Letters, 27 Aug. 2012. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.26>
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