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Compiler-Assisted, Selective Out-Of-Order Commit
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ISSN: 1556-6056
| ASCII Text | x | ||
| Nam Duong, Alex Veidenbaum, "Compiler-Assisted, Selective Out-Of-Order Commit," IEEE Computer Architecture Letters, vol. 99, no. 2, pp. , , 5555. | |||
| BibTex | x | ||
| @article{ 10.1109/L-CA.2012.8, author = {Nam Duong and Alex Veidenbaum}, title = {Compiler-Assisted, Selective Out-Of-Order Commit}, journal ={IEEE Computer Architecture Letters}, volume = {99}, number = {2}, issn = {1556-6056}, year = {5555}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.8}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - IEEE Computer Architecture Letters TI - Compiler-Assisted, Selective Out-Of-Order Commit IS - 2 SN - 1556-6056 SP EP EPD - A1 - Nam Duong, A1 - Alex Veidenbaum, PY - 5555 KW - RISC/CISC KW - VLIW architectures KW - Pipeline processors KW - Von Neumann architectures KW - Hardware/software interfaces KW - Superscalar KW - dynamically-scheduled KW - and statically-scheduled implementation KW - Pipeline implementation VL - 99 JA - IEEE Computer Architecture Letters ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.8
This paper proposes an out-of-order instruction commit mechanism using a novel compiler/architecture interface. The compiler creates instruction “blocks” guaranteeing some commit conditions and the processor uses the block information to commit certain instructions out of order. Micro-architectural support for the new commit mode is made on top of the standard, ROB-based processor and includes out-of-order instruction commit with register and load queue entry release. The commit mode may be switched multiple times during execution. Initial results for a 4-wide processor show that, on average, 52% instructions are committed out of order resulting in 10% to 26% speedups over in-order commit, with minimal hardware overhead. The performance improvement is a result of an effectively larger instruction window that allows more cache misses to be overlapped for both L1 and L2 caches.
Index Terms:
RISC/CISC, VLIW architectures, Pipeline processors, Von Neumann architectures, Hardware/software interfaces, Superscalar, dynamically-scheduled, and statically-scheduled implementation, Pipeline implementation
Citation:
Nam Duong, Alex Veidenbaum, "Compiler-Assisted, Selective Out-Of-Order Commit," IEEE Computer Architecture Letters, 18 May 2012. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.8>
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