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Issue No.01 - Jan.-June (2014 vol.13)
pp: 41-44
Shahar Kvatinsky , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa, Israel
Yuval H. Nacson , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa, Israel
Yoav Etsion , Electrical Engineering and Computer Science Departments, Technion - Israel Institute of Technology, Haifa, Israel
Eby G. Friedman , Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY
Avinoam Kolodny , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa, Israel
Uri C. Weiser , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa, Israel
ABSTRACT
Switch on Event Multithreading (SoE MT, also known as coarse-grained MT and block MT) processors run multiple threads on a pipeline machine, while the pipeline switches threads on stall events (e.g., cache miss). The thread switch penalty is determined by the number of stages in the pipeline that are flushed of in-flight instructions. In this paper, Continuous Flow Multithreading (CFMT), a new architecture of SoE MT, is introduced. In CFMT, a multistate pipeline register (MPR) holds the microarchitectural state of multiple different threads within the execution pipeline stages, where only one thread is active at a time. The MPRs eliminate the need to flush in-flight instructions and therefore significantly improve performance. In recent years, novel memory technologies such as Resistive RAM (RRAM) and Spin Torque Transfer Magnetoresistive RAM (STT-MRAM), have been developed. All of these technologies are nonvolatile, store data as resistance, and can be described as “memristors.” Memristors are power efficient, dense, and fast as compared to standard memory technologies such as SRAM, DRAM, and Flash. Memristors therefore provide the opportunity to place the MPRs physically within the pipeline stages. A performance analysis of CFMT is compared to conventional SoE MT processors, demonstrating up to a 2X performance improvement, while the operational mechanism, due to the use of memristors, is low power and low complexity as compared to conventional SoE MT processors.
INDEX TERMS
C.0.d Modeling of computer architecture, B Hardware, B.3 Memory Structures, B Hardware, B.7 Integrated Circuits, B.7.1 Types and Design Styles, B.7.1.e Memory technologies, C Computer Systems Organization, C.0 General, C.0.a Emerging technologies, C Computer Systems Organization, C.0 General,STT-MRAM, memristor, multithreaded processors, phase change memory, RRAM
CITATION
Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser, "Memristor-Based Multithreading", IEEE Computer Architecture Letters, vol.13, no. 1, pp. 41-44, Jan.-June 2014, doi:10.1109/L-CA.2013.3
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