Issue No.01 - Jan.-June (2014 vol.13)
Emilio G. Cota , , Columbia University
Paolo Mantovani , , Columbia University
Michele Petracca , , Cadence Design Systems Inc.
Mario R. Casu , , Politecnico di Torino
Luca P. Carloni , , Columbia University
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2012.29
Accelerators integrated on-die with General-Purpose CPUs (GP-CPUs) can yield significant performance and power improvements. Their extensive use, however, is ultimately limited by their area overhead; due to their high degree of specialization, the opportunity cost of investing die real estate on accelerators can become prohibitive, especially for general-purpose architectures. In this paper we present a novel technique aimed at mitigating this opportunity cost by allowing GP-CPU cores to
reuse accelerator memory as a non-uniform cache architecture (NUCA) substrate. On a system with a last level-2 cache of 128kB, our technique achieves on average a 25% performance improvement when reusing four 512 kB accelerator memory blocks to form a level-3 cache. Making these blocks reusable as NUCA slices incurs on average in a 1.89% area overhead with respect to equally-sized ad hoc cache slices.
Transform coding, Tiles, Silicon, Acceleration, Memory management, Power demand,Accelerator architectures, Cache memory,accelerator architectures, Cache memory
Emilio G. Cota, Paolo Mantovani, Michele Petracca, Mario R. Casu, Luca P. Carloni, "Accelerator Memory Reuse in the Dark Silicon Era", IEEE Computer Architecture Letters, vol.13, no. 1, pp. 9-12, Jan.-June 2014, doi:10.1109/L-CA.2012.29