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Issue No.02 - July-Dec. (2013 vol.12)
pp: 67-70
Priyanka Tembey , Georgia Institute of Technology, Atlanta
Augusto Vega , IBM T.J.Watson Research Center, Yorktown Heights
Alper Buyuktosunoglu , IBM T.J. Watson Research Center, Yorktown Heights
Dilma Da Silva , IBM T.J. Watson Research Center, Yorktown Heights
Pradip Bose , IBM T.J. Watson Research Center, Yorktown Heights
Simultaneous multithreading (SMT) as a processor design to achieve higher levels of system and application throughput is a well-accepted and deployed technique in most desktop and server processors. We study the power implications of varying SMT levels i.e., thread counts per core for various multi-threaded applications on a real SMT multicore platform, and introduce a novel software mechanism of changing SMT level of a core to tune platform power. Power-shifting policies by varying per core SMT levels for performance benefits within a power cap are introduced. Projected power savings (of 15%) for a streaming parallel benchmark can be attained using SMT-level power shifting mechanisms.
Power system management, Computer architecture, Program processors, Software engineering, Multithreading, Parallel processing,Scheduling, Hardware, Power Management, Computer Systems Organization, Processor Architectures, Other Architecture Styles, Multithreaded processors, Software/Software Engineering, Operating Systems, Process Management
Priyanka Tembey, Augusto Vega, Alper Buyuktosunoglu, Dilma Da Silva, Pradip Bose, "SMT Switch: Software Mechanisms for Power Shifting", IEEE Computer Architecture Letters, vol.12, no. 2, pp. 67-70, July-Dec. 2013, doi:10.1109/L-CA.2012.26
1. A. Mishra,S. Shrikanthaiah et al, “CPM in CMPs: Coordinated power management in CMPs?” , SC'10, Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.
2. C. Lefurgy,X. Wang,M. Ware., Server-Level Power Control. In Proceedings of the 4th International Conference on Autonomic Computing, ICAC pages 414, 2007.
3. C. Lefurgy,X. Wang,M. Ware,“Power capping: A prelude to power-shifting,” Journal of Cluster Computing, vol. 11, no. 2, pp. 183-195, June 2008
4. C. Bienia,S. Kumar,J. Pal Singh,K. Li,“The PARSEC Benchmark Suite: Characterization and Architectural Implications,” Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, October 2008
5. D. Tullsen,S. Eggers,H. Levy,“Simultaneous multithreading: Maximizing on-chip parallelism,” 25 Years ISCA: Retrospectives and Reprints, 1998 pp. 533–544
6. L. McDowell,S. Eggers,S. Gribble,“Improving server software support for simultaneous multithreaded processors,” Proceedings of the ninth ACM SIGPLAN symposium on Principles and practice of parallel programming, June 2003
7. M. Chen,X. Wang,X. Li,“Coordinating Processor and Main Memory for Efficient Server Power Control” ICS 2011, Proceedings of the 2011 International Conference on Supercomputing
8. M. Floyd,M. Allen-Ware,K. Rajamani,B. Brock,C. Lefurgy,A. J. Drake,L. Pesantez,T. Gloekler,J. A. Tierno,P. Bose,A. Buyukto-sunoglu., Introducing the Adaptive Energy Management Features of the POWER7 Chip. IEEE Micro, 31(2):60-75, March–April 2011.
9. S. Eyerman,K. Du Bois, et al, Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications. , IEEE Symposium on Performance Analysis of Systems and Software (ISPASS), 2012.
10. W. Felter,K. Rajamani,T. Keller et al “A Performance-Conserving Approach For Reducing Peak Power Consumption in Server Systems,” ICS 2005, Proceedings of the 2005 International Conference on Supercomputing
11. X. Wang,K. Ma et al, “Adaptive Power control with online model estimation for Chip Multiprocessors,” , IEEE TPDS 2011, Journal of IEEE Transactions on Parallel and Distributed Systems.
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