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Multicore Model from Abstract Single Core Inputs
July-Dec. 2013 (vol. 12 no. 2)
pp. 59-62
Emily Blem, UW - Madison, Madison
Hadi Esmaeilzadeh, University of Washington, Seattle
Renee St. Amant, The University of Texas at Austin, Austin
Karthikeyan Sankaralingam, UW-Madison, Madison
Doug Burger, Microsoft Research, Redmond
This paper describes a first order multicore model to project a tighter upper bound on performance than previous Amdahl's Law based approaches. The speedup over a known baseline is a function of the core performance, microarchitectural features, application parameters, chip organization, and multicore topology. The model is flexible enough to consider both CPU and GPU like organizations as well as modern topologies from symmetric to aggressive heterogeneous (asymmetric, dynamic, and fused) designs. This extended model incorporates first order effect exposing more bottlenecks than previous applications of Amdahl's Law while remaining simple and flexible enough to be adapted for many applications.
Index Terms:
Multiple Data Stream Architectures (Multiprocessors),Computer Systems Organization,General,Modeling of computer architecture,Computer Systems Organization,Processor Architectures
Emily Blem, Hadi Esmaeilzadeh, Renee St. Amant, Karthikeyan Sankaralingam, Doug Burger, "Multicore Model from Abstract Single Core Inputs," IEEE Computer Architecture Letters, vol. 12, no. 2, pp. 59-62, July-Dec. 2013, doi:10.1109/L-CA.2012.27
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