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Issue No.02 - July-Dec. (2013 vol.12)
pp: 47-50
Hanjoon Kim , KAIST, Daejeon
Yonggon Kim , KAIST, Daejeon
John Kim , KAIST, Daejeon
Bufferless on-chip networks are an alternative type of on-chip network organization that can improve the cost-efficiency of an on-chip network by removing router input buffers. However, bufferless on-chip network performance degrades at high load because of the increased network contention and large number of deflected packets. The energy benefit of bufferless network is also reduced because of the increased deflection. In this work, we propose a novel flow control for bufferless on-chip networks in high-throughput manycore accelerator architectures to reduce the impact of deflection routing. By using a clumsy flow control (CFC), instead of the per-hop flow control that is commonly used in buffered on-chip networks, we are able to reduce the amount of deflection by up to 92% on high-throughput workloads. As a result, on average, CFC can approximately match the performance of a baseline buffered router while reducing the energy consumption by approximately 39%.
Computer architecture, Multiprocessing systems, Parallel architectures, System-on-chip, Data processing,Parallel Architectures, On-chip interconnection networks, Computer Systems Organization, Processor Architectures, Multiple Data Stream Architectures (Multiprocessors), Interconnection architectures, Computer Systems Organization, Processor Architectures
Hanjoon Kim, Yonggon Kim, John Kim, "Clumsy Flow Control for High-Throughput Bufferless On-Chip Networks", IEEE Computer Architecture Letters, vol.12, no. 2, pp. 47-50, July-Dec. 2013, doi:10.1109/L-CA.2012.22
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