This Article 
 Bibliographic References 
 Add to: 
High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity
July-Dec. 2013 (vol. 12 no. 2)
pp. 39-42
Xun Jian, UIUC Xun Jian, Champaign
John Sartori, UIUC, Champaign
Henry Duwe, UIUC, Champaign
Rakesh Kumar, UIUC, Champaign
It is well-known that a significant fraction of server power is consumed in memory; this is especially the case for servers with chipkill correct memories. We propose a new chipkill correct memory organization that decouples correction of errors due to local faults that affect a single symbol in a word from correction of errors due to device-level faults that affect an entire column, sub-bank, or device. By using a combination of two codes that separately target these two fault modes, the proposed chipkill correct organization reduces code overhead by half as compared to conventional chipkill correct memories for the same rank size. Alternatively, this allows the rank size to be reduced by half while maintaining roughly the same total code overhead. Simulations using PARSEC and SPEC benchmarks show that, compared to a conventional double chipkill correct baseline, the proposed memory organization, by providing double chipkill correct at half the rank size, reduces power by up to 41%, 32% on average over a conventional baseline with the same chipkill correct strength and access granularity that relies on linear block codes alone, at only 1% additional code overhead.
Index Terms:
DRAM chips,Random access memory,Low power electronics,Servers,Computer architecture,DRAM,chipkill correct,low power,reliable memory
Xun Jian, John Sartori, Henry Duwe, Rakesh Kumar, "High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity," IEEE Computer Architecture Letters, vol. 12, no. 2, pp. 39-42, July-Dec. 2013, doi:10.1109/L-CA.2012.21
Usage of this product signifies your acceptance of the Terms of Use.