The Community for Technology Leaders
RSS Icon
Issue No.01 - January-June (2013 vol.12)
pp: 25-28
S. Nilakantan , Electr. & Comput. Eng. Dept., Drexel Univ., Philadelphia, PA, USA
S. Battle , Electr. & Comput. Eng. Dept., Drexel Univ., Philadelphia, PA, USA
M. Hempstead , Electr. & Comput. Eng. Dept., Drexel Univ., Philadelphia, PA, USA
The term “Dark Silicon” has been coined to describe the threat to microprocessor performance caused by increasing transistor power density. Improving energy efficiency is now the primary design goal for all market segments of microprocessors from mobile to server. Specialized hardware accelerators, designed to run only a subset of workloads with orders of magnitude energy efficiency improvement, are seen as a potential solution. Selecting an ensemble of accelerators to best cover the workloads run on a platform remains a challenge. We propose metrics for accelerator selection derived from a detailed communication-aware performance model and present an automated methodology to populate this model. Employing a combination of characterized RTL and our selection metrics, we evaluate a set of accelerators for a sample application and compare performance to selections based on execution time and Pollack's rule. We find that the architecture selected by our communication-aware metric shows improved performance over architectures selected based on execution time and Pollack's rule, as they do not account for speedup being limited by communication.
Computer architecture, Program processors, Multiprocessing systems, Accelerators, Modeling,Heterogeneous Architectures, Computer Systems Organization, General, Modeling of computer architecture, Computer Systems Organization, Processor Architectures, Other Architecture Styles, Heterogeneous (hybrid) systems, Code Profiling, Accelerators
S. Nilakantan, S. Battle, M. Hempstead, "Metrics for Early-Stage Modeling of Many-Accelerator Architectures", IEEE Computer Architecture Letters, vol.12, no. 1, pp. 25-28, January-June 2013, doi:10.1109/L-CA.2012.9
1. E. Chung et at, “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?” in MICRO 2010.
2. R. H. Dennard et al., “Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,” IEEE Journal of Solid-State Circuits, vol. SC, no. 9, pp. 256-268, October 1974.
3. R. Ernst,J. Henkel,, and T. Benner,“Hardware-software cosynthesis for microcontrollers,” IEEE Des. Test, vol. 10, no. 4, 1993.
4. H. Esmaeilzadeh, et al, “Dark Silicon and the End of Multicore Scaling,” in ISCA 38, 2011, June 2011.
5. M. Galanis et al, “Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware,” in ASAP 2005, July 2005.
6. C. Gremzow,“Compiled low-level virtual instruction set simulation and profiling for code partitioning and asip-synthesis in hardware/software co-design,” in Proceedings of SCSC 2007.
7. R. K. Gupta and G. De Micheli,“Hardware-software cosynthesis for digital systems,” IEEE Des. Test, vol. 10, no. 3, 1993.
8. B. Holland et al., “RAT: a methodology for predicting performance in application design migration to fpgas,” in HPRCTA'07, 2007.
9. M. Huang et al, “Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing,” ACM Trans. Reconfigurable Technol. Syst., vol. 3, no. 4, Nov. 2010.
10. P.-A. Mudry et al., “A dynamically constrained genetic algorithm for hardware-software partitioning,” in Proceedings of GECCO 2006.
11. N. Nethercote and J. Seward,“Valgrind: a framework for heavyweight dynamic binary instrumentation,” in Proceedings of PLDI 2007.
12. OpenCores, “OpenCores,” http:/
13. F. J. Pollack,“New microarchitecture challenges in the coming generations of CMOS process technologies (keynote) ” in MICRO 32, 1999.
14. M. C. Smith and G. D. Peterson,“Parallel application performance on shared high performance reconfigurable computing resources,” Perform. Eval, vol. 60, no. 1-4, May 2005.
15. Spiral Project, “Software/Hardware generation for DSP algorithms,” http:/
16. D. Terpstra,H. Jagode,H. You,, and J. Dongarra,“Collecting performance data with PAPI-C,” Tools for High Performance Computing, 2009.
17. G. Venkatesh et al., “Conservation cores: reducing the energy of mature computations,” in Proceedings of ASPLOS 15, 2010.
18. H. Youness et al., “A high performance algorithm for scheduling and hardware-software partitioning on mpsocs,” in DTIS 2009, April 2009.
105 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool