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Issue No.01 - January-June (2013 vol.12)
pp: 25-28
S. Nilakantan , Electr. & Comput. Eng. Dept., Drexel Univ., Philadelphia, PA, USA
S. Battle , Electr. & Comput. Eng. Dept., Drexel Univ., Philadelphia, PA, USA
M. Hempstead , Electr. & Comput. Eng. Dept., Drexel Univ., Philadelphia, PA, USA
ABSTRACT
The term “Dark Silicon” has been coined to describe the threat to microprocessor performance caused by increasing transistor power density. Improving energy efficiency is now the primary design goal for all market segments of microprocessors from mobile to server. Specialized hardware accelerators, designed to run only a subset of workloads with orders of magnitude energy efficiency improvement, are seen as a potential solution. Selecting an ensemble of accelerators to best cover the workloads run on a platform remains a challenge. We propose metrics for accelerator selection derived from a detailed communication-aware performance model and present an automated methodology to populate this model. Employing a combination of characterized RTL and our selection metrics, we evaluate a set of accelerators for a sample application and compare performance to selections based on execution time and Pollack's rule. We find that the architecture selected by our communication-aware metric shows improved performance over architectures selected based on execution time and Pollack's rule, as they do not account for speedup being limited by communication.
INDEX TERMS
Computer architecture, Program processors, Multiprocessing systems, Accelerators, Modeling,Heterogeneous Architectures, Computer Systems Organization, General, Modeling of computer architecture, Computer Systems Organization, Processor Architectures, Other Architecture Styles, Heterogeneous (hybrid) systems, Code Profiling, Accelerators
CITATION
S. Nilakantan, S. Battle, M. Hempstead, "Metrics for Early-Stage Modeling of Many-Accelerator Architectures", IEEE Computer Architecture Letters, vol.12, no. 1, pp. 25-28, January-June 2013, doi:10.1109/L-CA.2012.9
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