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Shrink-Fit: A Framework for Flexible Accelerator Sizing
January-June 2013 (vol. 12 no. 1)
pp. 17-20
RTL design complexity discouraged adoption of reconfigurable logic in general purpose systems, impeding opportunities for performance and energy improvements. Recent improvements to HLS compilers simplify RTL design and are easing this barrier. A new challenge will emerge: managing reconfigurable resources between multiple applications with custom hardware designs. In this paper, we propose a method to "shrink-fit" accelerators within widely varying fabric budgets. Shrink-fit automatically shrinks existing accelerator designs within small fabric budgets and grows designs to increase performance when larger budgets are available. Our method takes advantage of current accelerator design techniques and introduces a novel architectural approach based on fine-grained virtualization. We evaluate shrink-fit using a synthesized implementation of an IDCT for decoding JPEGs and show the IDCT accelerator can shrink by a factor of 16x with minimal performance and area overheads. Using shrink-fit, application designers can achieve the benefits of hardware acceleration with single RTL designs on FPGAs large and small.
Index Terms:
virtualisation,computational complexity,discrete cosine transforms,field programmable gate arrays,general purpose computers,inverse transforms,program compilers,reconfigurable architectures,temporal logic,virtual machines,flexible accelerator sizing,FPGA,hardware acceleration,IDCT accelerator,JPEG decoding,shrink fit accelerator,fine grained virtualization,reconfigurable architectural approach,fabric budget,custom hardware design,reconfigurable resource management,RTL design complexity,HLS compiler,general purpose system,reconfigurable logic,Accelerators,Field programmable gate arrays,Program processors,Computer applications,Decoding,Runtime,Special-Purpose and Application-Based Systems,Heterogeneous (hybrid) systems,Reconfigurable hardware
Citation:
M. Lyons, Gu-Yeon Wei, D. Brooks, "Shrink-Fit: A Framework for Flexible Accelerator Sizing," IEEE Computer Architecture Letters, vol. 12, no. 1, pp. 17-20, Jan.-June 2013, doi:10.1109/L-CA.2012.7
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