The Community for Technology Leaders
RSS Icon
Issue No.01 - January-June (2013 vol.12)
pp: 13-16
I. B. Karsli , TOBB Univ. of Econ. & Technol., Ankara, Turkey
P. Reviriego , Univ. Antonio de Nebrija, Madrid, Spain
M. F. Balli , TOBB Univ. of Econ. & Technol., Ankara, Turkey
O. Ergin , TOBB Univ. of Econ. & Technol., Ankara, Turkey
J. A. Maestro , Univ. Antonio de Nebrija, Madrid, Spain
Soft errors are transient errors that can alter the logic value of a register bit causing data corruption. They can be caused by radiation particles such as neutrons or alpha particles. Narrow values are commonly found in the data consumed or produced by processors. Several techniques have recently been proposed to exploit the unused bits in narrow values to protect them against soft errors. These techniques replicate the narrow value over the unused register bits such that errors can be detected when the value is duplicated and corrected when the value is tripled. In this letter, a technique that can correct errors when the narrow value is only duplicated is presented. The proposed approach stores a modified duplicate of the narrow value such that errors on the original value and the duplicate can be distinguished and therefore corrected. The scheme has been implemented at the circuit level to evaluate its speed and also at the architectural level to assess the benefits in correcting soft errors. The results show that the scheme is significantly faster than a parity check and can improve substantially the number of soft errors that are corrected compared to existing techniques.
Data processing, Registers, Logic gates, Program processors, Error correction, Parity check codes, Benchmark testing,Redundant design, Redundant design, Error-checking, Redundant design
I. B. Karsli, P. Reviriego, M. F. Balli, O. Ergin, J. A. Maestro, "Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values", IEEE Computer Architecture Letters, vol.12, no. 1, pp. 13-16, January-June 2013, doi:10.1109/L-CA.2012.6
1. R. C. Baumann,“Soft errors in advanced computer systems”, IEEE Des. Test. Comput., vol. 22, no. 3, pp. 258-266, May/Jun. 2005.
2. D. Brooks and M. Martonosi,“Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance”, Proc. Int'l Symp. High-Performance Computer Architecture (HPCA), 1999.
3. O. Ergin,O. Unsal,X. Vera,, and A. González,“Exploiting Narrow Values for Soft Error Tolerance”, IEEE Computer Architecture Letters (CAL'06), vol. 5, 2006.
4. O. Ergin,O. Unsal,X. Vera, and A. Gonzalez,“Reducing Soft Errors through Operand Width Aware Policies”, IEEE Transactions on Dependable and Secure Computing, vol. 6, issue, 3, July-Sept. 2009.
5. J. Hu,S. Wang,, and S.G. Ziavras,“In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability”, Proc. Int'l Conf. Dependable Systems and Networks (DSN), 2006.
6. J. J. Metzner,“Convolutionally Encoded Memory Protection”, IEEE Transactions on Computers, vol 31, no 6, pp. 547-551, 1983.
7. M. Nicolaidis,“Design for Soft Error Mitigation”, IEEE Transactions on Device and Materials Reliability, Vol. 5, No. 3, September 2005.
8. S. K. Reinhardt,S. S. Mukherjee,, and J. Emer,“The Soft Error Problem: An Architectural Perspective”, 11th International Symposium on High-Performance Computer Architecture (HPCA), 2005.
9. R.D. Schrimpf and D. M. Fleetwood, “Radiation effects in integrated circuits and electronic devices”, World Scientific Publishing, 2004.
10. J. Sharkey,“M-Sim: A Flexible, Multithreaded Architectural Simulation Environment”, Technical Report CS-TR-05-DP01, Dept. of CS, SUNY - Binghamton, October 2005.
11. C. Wilkerson,A. R. Alameldeen,Z. Chishti,W. Wu,D. Somasekhar,, and S. Lu,“Reducing Cache Power with Low Cost, Multi-bit Error-Correcting Codesℍ, International Symposium on Computer Architecture, pp. 83-93, Jun. 2010.
72 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool