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Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors
July-Dec. 2012 (vol. 11 no. 2)
pp. 49-52
Yang Li, University of Pittsburgh, Pittsburgh
Rami Melhem, University of Pittsburgh, Pittsburgh
Alex K. Jones, University of Pittsburgh, Pittsburgh
Traversing page table during virtual to physical address translation causes significant pipeline stalls when misses occur in the translation-lookaside buffer (TLB). To mitigate this penalty, we propose a fast, scalable, multi-level TLB organization that leverages page sharing behaviors and performs efficient TLB entry placement. Our proposed partial sharing TLB (PSTLB) reduces TLB misses by around 60%. PSTLB also improves TLB performance by nearly 40% compared to traditional private TLBs and 17% over the state of the art scalable TLB proposal.
Index Terms:
Prefetching,Benchmark testing,Virtual private networks,Runtime,Partial Sharing,Prefetching,Benchmark testing,Tiles,Oceans,Virtual private networks,Runtime,Fluids,CMPs,TLBs
Citation:
Yang Li, Rami Melhem, Alex K. Jones, "Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors," IEEE Computer Architecture Letters, vol. 11, no. 2, pp. 49-52, July-Dec. 2012, doi:10.1109/L-CA.2011.35
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