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Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures
July-Dec. 2012 (vol. 11 no. 2)
pp. 37-40
ASCII Text
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Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Xiaowen Chen, Hu Chen, Haibo Wang, "Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures," IEEE Computer Architecture Letters, vol. 11, no. 2, pp. 37-40, July-Dec., 2012.
 
 
BibTex
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@article{ 10.1109/L-CA.2011.34,
author = {Yaohua Wang and Shuming Chen and Kai Zhang and Jianghua Wan and Xiaowen Chen and Hu Chen and Haibo Wang},
title = {Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures},
journal ={IEEE Computer Architecture Letters},
volume = {11},
number = {2},
issn = {1556-6056},
year = {2012},
pages = {37-40},
doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.34},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - IEEE Computer Architecture Letters
TI - Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures
IS - 2
SN - 1556-6056
SP37
EP40
EPD - 37-40
A1 - Yaohua Wang,
A1 - Shuming Chen,
A1 - Kai Zhang,
A1 - Jianghua Wan,
A1 - Xiaowen Chen,
A1 - Hu Chen,
A1 - Haibo Wang,
PY - 2012
KW - Instruction sets
KW - Process control
KW - Resource management
KW - Vectors
KW - Scalability
KW - SIMD
KW - Kernel
KW - Process control
KW - Resource management
KW - Vectors
KW - Scalability
KW - Arrays
KW - data dependent control-flow
KW - instruction shuffle
KW - instruction buffer array
VL - 11
JA - IEEE Computer Architecture Letters
ER -
 
Yaohua Wang, National University of Defence Technology, PR.China.
Shuming Chen, National University of Defence Technology, PR.China.
Kai Zhang, National University of Defence Technology, PR.China.
Jianghua Wan, National University of Defence Technology, PR.China.
Xiaowen Chen, National University of Defence Technology, PR.China.
Hu Chen, National University of Defence Technology, PR.China.
Haibo Wang, National University of Defence Technology, PR.China.
SIMD architectures are less efficient for applications with the diverse control-flow behavior, which can be mainly attributed to the requirement of the identical control-flow. In this paper, we propose a novel instruction shuffle scheme that features an efficient control-flow handling mechanism. The cornerstones are composed of a shuffle source instruction buffer array and an instruction shuffle unit. The shuffle unit can concurrently deliver instructions of multiple distinct control-flows from the instruction buffer array to eligible SIMD lanes. Our instruction shuffle scheme combines the best attributes of both the SIMD and MIMD execution paradigms. Experimental results show that, an average performance improvement of 86% can be achieved, at a cost of only 5.8% area overhead.
Index Terms:
Instruction sets,Process control,Resource management,Vectors,Scalability,SIMD,Kernel,Process control,Resource management,Vectors,Scalability,Arrays,data dependent control-flow,instruction shuffle,instruction buffer array
Citation:
Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Xiaowen Chen, Hu Chen, Haibo Wang, "Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures," IEEE Computer Architecture Letters, vol. 11, no. 2, pp. 37-40, July-Dec. 2012, doi:10.1109/L-CA.2011.34
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