This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function
July-Dec. 2012 (vol. 11 no. 2)
pp. 33-36
Nagesh B. Lakshminarayana, Georgia Institute of Technology, Atlanta
Jaekyu Lee, Georgia Institute of Technology, Atlanta
Hyesoon Kim, Georgia Institute of Technology, Atlanta
Jinwoo Shin, Georgia Institute of Technology, Atlanta
GPGPU architectures (applications) have several different characteristics compared to traditional CPU architectures (applications): highly multithreaded architectures and SIMD-execution behavior are the two important characteristics of GPGPU computing. In this paper, we propose a potential function that models the DRAM behavior in GPGPU architectures and a DRAM scheduling policy α-SJF policy to minimize the potential function. The scheduling policy essentially chooses between SJF and FR-FCFS at run-time based on the number of requests from each thread and whether the thread has a row buffer hit.
Index Terms:
Random access memory,Processor scheduling,Computer architecture,Benchmark testing,Mathematical model,Equations,Instruction sets,DRAM scheduling,Random access memory,Processor scheduling,Computer architecture,Benchmark testing,Mathematical model,Equations,Instruction sets,Potential function,GPGPU
Citation:
Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, Jinwoo Shin, "DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function," IEEE Computer Architecture Letters, vol. 11, no. 2, pp. 33-36, July-Dec. 2012, doi:10.1109/L-CA.2011.32
Usage of this product signifies your acceptance of the Terms of Use.