DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function

Nagesh B. Lakshminarayana; Jinwoo Shin; Jaekyu Lee; Hyesoon Kim

doi:10.1109/L-CA.2011.32

Computer Architecture Letters
2012
Issue No. 2 - July-Dec.
Abstract - DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function

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DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function

July-Dec. 2012 (vol. 11 no. 2)

pp. 33-36

	ASCII Text	x
	Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, Jinwoo Shin, "DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function," IEEE Computer Architecture Letters, vol. 11, no. 2, pp. 33-36, July-Dec., 2012.

	BibTex	x
	@article{ 10.1109/L-CA.2011.32, author = {Nagesh B. Lakshminarayana and Jaekyu Lee and Hyesoon Kim and Jinwoo Shin}, title = {DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function}, journal ={IEEE Computer Architecture Letters}, volume = {11}, number = {2}, issn = {1556-6056}, year = {2012}, pages = {33-36}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.32}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - IEEE Computer Architecture Letters TI - DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function IS - 2 SN - 1556-6056 SP33 EP36 EPD - 33-36 A1 - Nagesh B. Lakshminarayana, A1 - Jaekyu Lee, A1 - Hyesoon Kim, A1 - Jinwoo Shin, PY - 2012 KW - Random access memory KW - Processor scheduling KW - Computer architecture KW - Benchmark testing KW - Mathematical model KW - Equations KW - Instruction sets KW - DRAM scheduling KW - Random access memory KW - Processor scheduling KW - Computer architecture KW - Benchmark testing KW - Mathematical model KW - Equations KW - Instruction sets KW - Potential function KW - GPGPU VL - 11 JA - IEEE Computer Architecture Letters ER -

Nagesh B. Lakshminarayana, Georgia Institute of Technology, Atlanta

Jaekyu Lee, Georgia Institute of Technology, Atlanta

Hyesoon Kim, Georgia Institute of Technology, Atlanta

Jinwoo Shin, Georgia Institute of Technology, Atlanta

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.32

GPGPU architectures (applications) have several different characteristics compared to traditional CPU architectures (applications): highly multithreaded architectures and SIMD-execution behavior are the two important characteristics of GPGPU computing. In this paper, we propose a potential function that models the DRAM behavior in GPGPU architectures and a DRAM scheduling policy Î±-SJF policy to minimize the potential function. The scheduling policy essentially chooses between SJF and FR-FCFS at run-time based on the number of requests from each thread and whether the thread has a row buffer hit.

Index Terms:

Random access memory,Processor scheduling,Computer architecture,Benchmark testing,Mathematical model,Equations,Instruction sets,DRAM scheduling,Random access memory,Processor scheduling,Computer architecture,Benchmark testing,Mathematical model,Equations,Instruction sets,Potential function,GPGPU

Citation:

Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim, Jinwoo Shin, "DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function," IEEE Computer Architecture Letters, vol. 11, no. 2, pp. 33-36, July-Dec. 2012, doi:10.1109/L-CA.2011.32

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