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A High-Level Power Model for MPSoC on FPGA
Jan.-June 2012 (vol. 11 no. 1)
pp. 13-16
Roberta Piscitelli, University of Amsterdam, Amsterdam
Andy Pimentel, University of Amsterdam, Amsterdam
This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures. As a result, it is capable of achieving good evaluation performance, thereby making the technique highly useful in the context of early system-level design space exploration. We have integrated the power estimation technique in a system-level MPSoC synthesis framework. Using this framework, we have designed a range of different candidate MPSoC architectures and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

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Index Terms:
Simulation, Formal models, Performance Analysis and Design Aids
Roberta Piscitelli, Andy Pimentel, "A High-Level Power Model for MPSoC on FPGA," IEEE Computer Architecture Letters, vol. 11, no. 1, pp. 13-16, Jan.-June 2012, doi:10.1109/L-CA.2011.24
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