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Issue No.01 - Jan.-June (2012 vol.11)
pp: 13-16
Roberta Piscitelli , University of Amsterdam, Amsterdam
Andy Pimentel , University of Amsterdam, Amsterdam
ABSTRACT
This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures. As a result, it is capable of achieving good evaluation performance, thereby making the technique highly useful in the context of early system-level design space exploration. We have integrated the power estimation technique in a system-level MPSoC synthesis framework. Using this framework, we have designed a range of different candidate MPSoC architectures and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.
INDEX TERMS
Simulation, Formal models, Performance Analysis and Design Aids
CITATION
Roberta Piscitelli, Andy Pimentel, "A High-Level Power Model for MPSoC on FPGA", IEEE Computer Architecture Letters, vol.11, no. 1, pp. 13-16, Jan.-June 2012, doi:10.1109/L-CA.2011.24
REFERENCES
1. "http://pmbus.orgspecs.html."
2. S. D. J.-L. B. Atitallah,R. Niar,"MPSoC power estimation framework at transaction level modeling," ICM 2007.
3. N. Eisley,V. Soteriou,, and L. Peh,"High-level power analysis for multi-core chips," in CASES'06: Proc. of the 2006 int. conference on Compilers, architecture and synthesis for embedded systems, USA, 2006, pp. 389-400.
4. D. S. G. Beltrame and C. Silvano,"Multi-accuracy power and performance transaction-level modeling," in DATE'08: Proc. of the conference on Design, automation and test in Europe.
5. J. Hu and R. Marculescu,"Energy-aware mapping for tile-based noc architectures under performance constraints," in ASP-DAC'03: Proc. of the 2003 Asia and South Pacific Design Automation Conference, USA, 2003, pp. 233-239.
6. S. Koohi,M. Mirza-Aghatabar,S. Hessabi,, and M. Pedram,"High-level modeling approach for analyzing the effects of traffic models on power and throughput in mesh-based nocs," in VLSID'08: Proc. of the 21st Int. Conference on VLSI Design.
7. I. Lee,H. Kim,P. Yang,S. Yoo,E. Chung,K. Choi,J. Kong,, and S. Eo,"Powervip: Soc power estimation framework at transaction level," in Proc. of the 2006 ASP-DAC'06. IEEE Press, 2006.
8. M. Loghi,L. Benini,, and M. Poncino,"Power macromodeling of MPSoC message passing primitives," ACM Trans. Embed. Comput. Syst., vol. 6, no. 4, p. 31, 2007.
9. M. Monchiero,G. Palermo,C. Silvano,, and O. Villa,"A modular approach to model heterogeneous MPSoC at Cycle Level," in DSD '08: Proc. of the 2008 11th EUROMICRO Conf. on Digital System Design Architectures, Methods and Tools, 2008.
10. N. Muralimanohar,R. Balasubramonian,, and N. Jouppi,"Optimizing nuca organizations and wiring alternatives for large caches with cacti 6.0," in MICRO 40: Proc. of the 40th Annual IEEE/ACM Int. Symposium on Microarchitecture, 2007.
11. L. Ost,G. Guindani,L. Indrusiak,S. Maatta,, and F. Moraes,"Using abstract power estimation models for design space exploration in NoC-based MPSoC," IEEE Design and Test of Computers, vol. 99, no. PrePrints, 2010.
12. A. D. Pimentel,C. Erbas,, and S. Polstra,"A systematic approach to exploring embedded system architectures at multiple abstraction levels," IEEE Trans. Comput., vol. 55, no. 2, 2006.
13. R. Piscitelli and A. Pimentel,"A high-level power model for mpsoc on fpga," in Proc. of the 18th Reconfigurable Architectures Workshop (RAW '11), 2011.
14. P. Stralen and A. D. Pimentel,"A high-level microprocessor power modeling technique based on event signatures," in Proc. of the IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia '07), 2007.
15. M. Thompson,H. Nikolov et al., , "A framework for rapid system-level exploration, synthesis, and programming of multimedia MPSoCs," in Proc. of the IEEE/ACM int. conference on Hardware/software codesign and system synthesis, 2007.
16. A. Varma et al., "Accurate and fast system-level power modeling: An xscale-based case study," ACM Trans. Embed. Comput. Syst., vol. 6, no. 4, p. 26, 2007.
17. Xilinx, "http://www.xilinx.com/products/design\textunderscore tools/ logic\textunderscore design/ verificationxpower.htm."
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