The Community for Technology Leaders
RSS Icon
Issue No.01 - Jan.-June (2012 vol.11)
pp: 9-12
Abhishek Deb , UPC, Barcelona
Josep Maria Codina , Intel labs Barcelona, UPC, Barcelona
Antonio Gonzalez , Intel and UPC Intel labs Barcelona, UPC, Barcelona
In this paper, we propose a novel programmable functional unit (PFU) to accelerate general purpose application execution on a modern out-of-order x86 processor. Code is transformed and instructions are generated that run on the PFU using a co-designed virtual machine (Cd-VM). Results presented in this paper show that this HW/SW co-designed approach produces average speedups in performance of 29% in SPECFP and 19% in SPECINT, and up-to 55%, over modern out-of-order processor.
Hardware/software interfaces, Processor Architectures, Micro-architecture implementation considerations
Abhishek Deb, Josep Maria Codina, Antonio Gonzalez, "A HW/SW Co-designed Programmable Functional Unit", IEEE Computer Architecture Letters, vol.11, no. 1, pp. 9-12, Jan.-June 2012, doi:10.1109/L-CA.2011.23
1. "SSE extension : Intel IA 64 and IA-32 Architectures Software Developer's Manual," 1997.
2. A. Klaiber,"The technology behind Crusoe Processors," 2000.
3. A. Deb,J. Codina,, and A. González,"A Co-designed HW/SW Approach to General Purpose Program Acceleration using a Programmable Functional Unit," in IEEE 15th Workshop on Interaction between Compilers and Computer Architecture, 2011.
4. E. Fetzer,M. Gibson,A. Klein,N. Calick,C. Zhu,E. Busta,, and B. Mohammad,"A fully bypassed six-integer datapath and register file on the itanium-2 microprocessor," in IEEE Intl. Journal of Solid-State Circuits, 2002.
5. S. Palacharla,N. Jouppi,, and J. Smith,"Complexity-effective superscalar processors," in IEEE Intl. Symp. on Computer Architecture, 1997.
6. M. Yourst,"PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator," in IEEE Intl. Symp. on Performance Analysis of Systems and Software, 2007.
7. S. Hu and J. E. Smith,"Reducing startup time in co-designed virtual machines," in In Proc. of the 33rd Annual International Symposium on Computer Architecture, 2006.
8. K. Ebcioglu and E. Altman,"DAISY: Dynamic compilation for 100% architectural compatibility," in IEEE Intl. Symp. on Computer Architecture, 1997.
9. N. Clark,M. Kudlur,H. Park,S. Mahlke,, and K. Flautner,"Application-Specific Processing on a General-Purpose Core via Transparent Instruction set customization," in IEEE Intl. Symp. on Microarchitecture, 2004.
10. Z. Ye,A. Moshovos,S. Hauck,, and P. Banerjee,"CHIMAERA: A high-performance architecture with a tightly-coupled reconfigurable functional unit," in IEEE Intl. Symp. on Computer Architecture, 2000.
11. S. Yehia and O. Temam,"From sequences of dependent instructions to functions: An approach for improving performance without ILP or speculation," in IEEE Intl. Symp. on Computer Architecture, 2004.
12. S. Hu,I. Kim,M. Lipasti,, and J. Smith,"An approach for implementing efficient superscalar CISC processors," in IEEE Intl. Symp. on High-Performance Computer Architecture, 2006.
13. A. Deb,J. Codina,, and A. Gonzalez,"SoftHV : A HW/SW Co-designed Processor with Horizontal and Vertical Fusion," in Proceedings of the 8th ACM International Conference on Computing Frontiers, 2011.
6 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool