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Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor
July-December 2011 (vol. 10 no. 2)
pp. 45-48
Inseok Choi, University of Maryland, College Park
Minshu Zhao, University of Maryland, College Park
Xu Yang, University of Maryland, College Park
Donald Yeung, Maryland, College Park
This paper describes our experience with profiling and optimizing physical locality for the distributed shared cache (DSC) in Tilera's Tile multicore processor. Our approach uses the Tile Processor's hardware performance measurement counters (PMCs) to acquire page-level access pattern profiles. A key problem we address is imprecise PMC interrupts. Our profiling tools use binary analysis to correct for interrupt ``skid,'' thus pinpointing individual memory operations that incur remote DSC slice references and permitting us to sample their access patterns. We use our access pattern profiles to drive {\em page homing optimizations} for both heap and static data objects. Our experiments show we can improve physical locality for 5 out of 11 SPLASH2 benchmarks running on 32 cores, enabling 32.9\%--77.9\% of DSC references to target the local DSC slice. To our knowledge, this is the first work to demonstrate page homing optimizations on a real system.
Index Terms:
Multiple Data Stream Architectures (Multiprocessors), Multi-core/single-chip multiprocessors, Design studies
Citation:
Inseok Choi, Minshu Zhao, Xu Yang, Donald Yeung, "Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor," IEEE Computer Architecture Letters, vol. 10, no. 2, pp. 45-48, July-Dec. 2011, doi:10.1109/L-CA.2011.18
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