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Fault-Tolerant Vertical Link Design for Effective 3D Stacking
July-December 2011 (vol. 10 no. 2)
pp. 41-44
Carles Hernández, Universidad Politécnica de Valencia, Valencia
Antoni Roca, Universitat Politécnica de Valencia, Valencia
Jose Flich, Universitat Politécnica de Valencia, Valencia
Federico Silla, Universitat Politécnica de Valencia, Valencia
Jose Duato, Universitat Politécnica de Valencia, Valencia
Recently, 3D stacking has been proposed to alleviate the memory bandwidth limitation arising in chip multiprocessors (CMPs). As the number of integrated cores in the chip increases the access to external memory becomes the bottleneck, thus demanding larger memory amounts inside the chip. The most accepted solution to implement vertical links between stacked dies is by using Through Silicon Vias (TSVs). However, TSVs are exposed to misalignment and random defects compromising the yield of the manufactured 3D chip. A common solution to this problem is by over-provisioning, thus impacting on area and cost. In this paper, we propose a fault-tolerant vertical link design. With its adoption, fault-tolerant vertical links can be implemented in a 3D chip design at low cost without the need of adding redundant TSVs (no over-provision). Preliminary results are very promising as the fault-tolerant vertical link design increases switch area only by 6.69% while the achieved interconnect yield tends to 100%.
Index Terms:
NoC, 3D stacking, Fault Tolerance
Citation:
Carles Hernández, Antoni Roca, Jose Flich, Federico Silla, Jose Duato, "Fault-Tolerant Vertical Link Design for Effective 3D Stacking," IEEE Computer Architecture Letters, vol. 10, no. 2, pp. 41-44, July-Dec. 2011, doi:10.1109/L-CA.2011.17
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