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Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks
July-December 2011 (vol. 10 no. 2)
pp. 33-36
| ASCII Text | x | ||
| George Michelogiannakis, Nan Jiang, Daniel Becker, William Dally, "Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks," IEEE Computer Architecture Letters, vol. 10, no. 2, pp. 33-36, July-December, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/L-CA.2011.15, author = {George Michelogiannakis and Nan Jiang and Daniel Becker and William Dally}, title = {Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks}, journal ={IEEE Computer Architecture Letters}, volume = {10}, number = {2}, issn = {1556-6056}, year = {2011}, pages = {33-36}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.15}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - IEEE Computer Architecture Letters TI - Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks IS - 2 SN - 1556-6056 SP33 EP36 EPD - 33-36 A1 - George Michelogiannakis, A1 - Nan Jiang, A1 - Daniel Becker, A1 - William Dally, PY - 2011 KW - On-chip interconnection networks KW - Interconnection architectures VL - 10 JA - IEEE Computer Architecture Letters ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.15
This paper introduces packet chaining, a simple and effective method to increase allocator matching efficiency and hence network performance, particularly suited to networks with short packets and short cycle times. Packet chaining operates by chaining packets destined to the same output together, to reuse the switch connection of a departing packet. This allows an allocator to build up an efficient matching over a number of cycles, like incremental allocation, but not limited by packet length. For a 64-node 2D mesh at maximum injection rate and with single-flit packets, packet chaining increases network throughput by 15% compared to a conventional single-iteration separable iSLIP allocator, outperforms a wavefront allocator, and gives comparable throughput with an augmenting paths allocator. Packet chaining achieves this performance with a cycle time comparable to a single-iteration separable allocator. Packet chaining also reduces average network latency by 22.5%. Finally, packet chaining increases IPC up to 46% (16% average) for application benchmarks because short packets are critical in a typical cache-coherent CMP. These are considerable improvements given the maturity of network-on-chip routers and allocators.
Index Terms:
On-chip interconnection networks, Interconnection architectures
Citation:
George Michelogiannakis, Nan Jiang, Daniel Becker, William Dally, "Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks," IEEE Computer Architecture Letters, vol. 10, no. 2, pp. 33-36, July-Dec. 2011, doi:10.1109/L-CA.2011.15
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