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Exploiting SPMD Horizontal Locality
January-June 2011 (vol. 10 no. 1)
pp. 20-23
Chunyang Gou, Delft University of Technology, Delft
Georgi Gaydadjiev, Delft University of Technology, Delft
In this paper, we analyze a particular spatial locality case (called horizontal locality) inherent to manycore accelerator architectures employing barrel execution of SPMD kernels, such as GPUs. We then propose an adaptive memory access granularity framework to exploit and enforce the horizontal locality in order to reduce the interferences among accelerator cores memory accesses and hence improve DRAM efficiency. With the proposed technique, DRAM efficiency grows by 1.42X on average, resulting in 12.3% overall performance gain, for a set of representative memory intensive GPGPU applications.
Index Terms:
SIMD processors, Multi-core/single-chip multiprocessors, Memory hierarchy
Citation:
Chunyang Gou, Georgi Gaydadjiev, "Exploiting SPMD Horizontal Locality," IEEE Computer Architecture Letters, vol. 10, no. 1, pp. 20-23, Jan.-June 2011, doi:10.1109/L-CA.2011.5
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