Issue No.01 - January-June (2011 vol.10)
P Rosenfeld , Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD, USA
B Jacob , Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD, USA
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2011.4
In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model which can be used in both full system and trace-based simulations. We describe the process of validating DRAMSim2 timing against manufacturer Verilog models in an effort to prove the accuracy of simulation results. We outline the combination of DRAMSim2 with a cycle-accurate x86 simulator that can be used to perform full system simulations. Finally, we discuss DRAMVis, a visualization tool that can be used to graph and compare the results of DRAMSim2 simulations.
memory cards, DRAM chips, memory architecture, DRAMSim2 simulation, cycle accurate memory system simulator, DDR2/3 memory system model, trace-based simulation, DRAMSim2 timing, Verilog model, visualization tool, Object oriented modeling, Computational modeling, Random access memory, Timing, Hardware design languages, Load modeling, Driver circuits, Primary memory, DRAM, Simulation
P Rosenfeld, B Jacob, "DRAMSim2: A Cycle Accurate Memory System Simulator", IEEE Computer Architecture Letters, vol.10, no. 1, pp. 16-19, January-June 2011, doi:10.1109/L-CA.2011.4