Issue No.01 - January-June (2010 vol.9)
Hyungjun Kim , Texas A&M University, College Station
Paul Gratz , Texas A&M University, College Station
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2010.9
Power is of paramount importance in modern computer system design. In particular, the cache interconnect in future CMP designs is projected to consume up to half of the system power for cache fills and spills. Despite the power consumed by spills and fills, a significant percentage of each cache line is unused prior to eviction from the cache. If unused cache block words can be identified, this information can be used to improve CMP interconnect power and energy consumption. We propose a new method of CMP interconnect packet composition, leveraging unused data to reduce power. These methods are well suited to interconnection networks with high-bandwidth wires, and do not require expensive multi-ported memory systems. Assuming perfect prediction, our technique achieves an average of 37% savings in total dynamic link power consumption. With our current best prediction mechanism, our techniques reduce dynamic power consumption by 23% on average.
Cache memories, Interconnection architectures, Low-power design
Hyungjun Kim, Paul Gratz, "Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect", IEEE Computer Architecture Letters, vol.9, no. 1, pp. 33-36, January-June 2010, doi:10.1109/L-CA.2010.9