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A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
January-June 2010 (vol. 9 no. 1)
pp. 29-32
Mohammad Hammoud, Dept. of Comput. Sci., Univ. of Pittsburgh, Pittsburgh, PA, USA
Sangyeun Cho, Dept. of Comput. Sci., Univ. of Pittsburgh, Pittsburgh, PA, USA
Rami Melhem, Dept. of Comput. Sci., Univ. of Pittsburgh, Pittsburgh, PA, USA
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by the large non-uniform distribution of memory accesses across cache sets in different L2 banks. DPAP decouples the physical locations of cache blocks from their addresses for the sake of reducing misses caused by destructive interferences. Temporal pressure at the on-chip last-level cache, is continuously collected at a group (comprised of local cache sets) granularity, and periodically recorded at the memory controller(s) to guide the placement process. An incoming block is consequently placed at a cache group that exhibits the minimum pressure. Simulation results using a full-system simulator demonstrate that DPAP outperforms the baseline shared NUCA scheme by an average of 8.3% and by as much as 18.9% for the benchmark programs we examined. Furthermore, evaluations showed that DPAP outperforms related cache designs.
Index Terms:
microprocessor chips,cache storage,NUCA scheme,dynamic pressure aware associative placement strategy,large scale chip multiprocessors,DPAP,distributed cache management,memory access distribution,destructive interferences,memory controllers,Large-scale systems,Interference,Aggregates,Network-on-a-chip,Computer science,Random access memory,Pressure control,Computer architecture,Local Cache Sets,Chip Multiprocessors,Associative Placement,Pressure-Aware Placement,Aggregate Cache Sets
Citation:
Mohammad Hammoud, Sangyeun Cho, Rami Melhem, "A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors," IEEE Computer Architecture Letters, vol. 9, no. 1, pp. 29-32, Jan.-June 2010, doi:10.1109/L-CA.2010.7
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