Issue No.01 - January-June (2010 vol.9)
Andrew Hilton , University of Pennsylvania, Philadelphia
Amir Roth , University of Pennsylvania, Philadelphia
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2010.8
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any thread appear to occur in program order to all other threads. Out-of-order execution can violate load-load ordering. Multi-processors with out-of-order cores detect load-load ordering violations by snooping an age-ordered load queue on cache invalidations or evictions---events that act as proxies for the completion of remote stores. This mechanism becomes less efficient in an SMT, as every completing store must search the loads queue segments of all other threads. This inefficiency exists because store completions from other threads in the same core are not filtered by the cache: thread 0 observes all of thread 1's stores, not only the first store to every cache line. SMT-Directory eliminates this overhead by implementing the filtering traditionally provided by the cache in the cache itself. SMT-Directory adds a per-thread ``read'' bit to every cache line. When a load executes, it sets the bit corresponding to its thread. When a store completes, it checks the SMT-Directory bits of its cache line and searches the load queue segments only of those threads whose bits are set. As a result, local store completions trigger searches only for data that is actually shared.
Multithreaded processors, Memory hierarchy
Andrew Hilton, Amir Roth, "SMT-Directory: Efficient Load-Load Ordering for SMT", IEEE Computer Architecture Letters, vol.9, no. 1, pp. 25-28, January-June 2010, doi:10.1109/L-CA.2010.8