|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors
July-December 2009 (vol. 8 no. 2)
pp. 52-55
| ASCII Text | x | ||
| Enric Musoll, "A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors," IEEE Computer Architecture Letters, vol. 8, no. 2, pp. 52-55, July-December, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/L-CA.2009.48, author = {Enric Musoll}, title = {A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors}, journal ={IEEE Computer Architecture Letters}, volume = {8}, number = {2}, issn = {1556-6056}, year = {2009}, pages = {52-55}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.48}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - IEEE Computer Architecture Letters TI - A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors IS - 2 SN - 1556-6056 SP52 EP55 EPD - 52-55 A1 - Enric Musoll, PY - 2009 KW - On-chip interconnection networks KW - Multi-core/single-chip multiprocessors VL - 8 JA - IEEE Computer Architecture Letters ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.48
Process variations in advanced nodes introduce significant core-to-core performance differences in single-chip multi-core architectures. Isolating each core with its own frequency and voltage island helps improving the performance of the multi-core architecture by operating at the highest frequency possible rather than operating all the cores at the frequency of the slowest core. However, inter-core communication suffers from additional cross-clock-domain latencies that can offset the performance benefits. This work proposes the concept of the configurable, variable-size frequency and voltage domain, and it is described in the context of a tile-based, massive multi-core architecture.
Index Terms:
On-chip interconnection networks, Multi-core/single-chip multiprocessors
Citation:
Enric Musoll, "A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors," IEEE Computer Architecture Letters, vol. 8, no. 2, pp. 52-55, July-Dec. 2009, doi:10.1109/L-CA.2009.48
Usage of this product signifies your acceptance of the Terms of Use.