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A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors
July-December 2009 (vol. 8 no. 2)
pp. 52-55
Enric Musoll, ConSentry Networks, Milpitas
Process variations in advanced nodes introduce significant core-to-core performance differences in single-chip multi-core architectures. Isolating each core with its own frequency and voltage island helps improving the performance of the multi-core architecture by operating at the highest frequency possible rather than operating all the cores at the frequency of the slowest core. However, inter-core communication suffers from additional cross-clock-domain latencies that can offset the performance benefits. This work proposes the concept of the configurable, variable-size frequency and voltage domain, and it is described in the context of a tile-based, massive multi-core architecture.
Index Terms:
On-chip interconnection networks, Multi-core/single-chip multiprocessors
Citation:
Enric Musoll, "A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors," IEEE Computer Architecture Letters, vol. 8, no. 2, pp. 52-55, July-Dec. 2009, doi:10.1109/L-CA.2009.48
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