Issue No.02 - July-December (2009 vol.8)
Enric Musoll , ConSentry Networks, Milpitas
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.48
Process variations in advanced nodes introduce significant core-to-core performance differences in single-chip multi-core architectures. Isolating each core with its own frequency and voltage island helps improving the performance of the multi-core architecture by operating at the highest frequency possible rather than operating all the cores at the frequency of the slowest core. However, inter-core communication suffers from additional cross-clock-domain latencies that can offset the performance benefits. This work proposes the concept of the configurable, variable-size frequency and voltage domain, and it is described in the context of a tile-based, massive multi-core architecture.
On-chip interconnection networks, Multi-core/single-chip multiprocessors
Enric Musoll, "A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors", IEEE Computer Architecture Letters, vol.8, no. 2, pp. 52-55, July-December 2009, doi:10.1109/L-CA.2009.48