Issue No.02 - July-December (2009 vol.8)
Ramachandra Kallam , Utah State University, Logan
Aravind Dasu , Utah State University, Logan
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2009.49
Partial bitstream relocation (PBR) on FPGAs has been gaining attention in recent years as a potentially promising technique to scale parallelism of accelerator architectures at run time, enhance fault tolerance, etc. PBR techniques to date have focused on reading inactive bitstreams stored in memory, on-chip or off-chip, whose contents are generated for a specific partial reconfiguration region (PRR) and modified on demand for configuration into a PRR at a different location. As an alternative, we propose a PRR-PRR relocation technique to generate source and destination addresses, read the bitstream from an active PRR (source) in a non-intrusive manner, and write it to destination PRR. We describe two options of realizing this on Xilinx Virtex 4 FPGAs: (a) hardware-based accelerated relocation circuit (ARC) and (b) a software solution executed on Microblaze. A comparative performance analysis to highlight the speed-up obtained using ARC is presented. For real test cases, performance of our implementations are compared to estimated performances of two state of the art methods.
Reconfigurable hardware, Emerging technologies, Performance Analysis and Design Aids
Ramachandra Kallam, Aravind Dasu, "PRR-PRR Dynamic Relocation", IEEE Computer Architecture Letters, vol.8, no. 2, pp. 44-47, July-December 2009, doi:10.1109/L-CA.2009.49