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Exploiting Locality to Improve Circuit-Level Timing Speculation
July-December 2009 (vol. 8 no. 2)
pp. 40-43
Jing Xin, Northwestern University, Evanston
Russ Joseph, Northwestern University, Evanston
Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins, eliminating power and performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. This work has not evaluated or exploited the disparity of error rates at the level of static instructions. In this paper, we demonstrate pronounced locality in error rates at the level of static instructions. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and reduce the costly recovery penalty. This allows us to achieve 43.6% power savings when compared to a baseline policy and incurs only 6.9% performance penalty.
Index Terms:
Reliability, Testing, and Fault-Tolerance, Low-power design
Citation:
Jing Xin, Russ Joseph, "Exploiting Locality to Improve Circuit-Level Timing Speculation," IEEE Computer Architecture Letters, vol. 8, no. 2, pp. 40-43, July-Dec. 2009, doi:10.1109/L-CA.2009.50
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