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DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals
July-December 2008 (vol. 7 no. 2)
pp. 65-68
| ASCII Text | x | ||
| Amit Golander, Shlomo Weiss, Ronny Ronen, "DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals," IEEE Computer Architecture Letters, vol. 7, no. 2, pp. 65-68, July-December, 2008. | |||
| BibTex | x | ||
| @article{ 10.1109/L-CA.2008.12, author = {Amit Golander and Shlomo Weiss and Ronny Ronen}, title = {DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals}, journal ={IEEE Computer Architecture Letters}, volume = {7}, number = {2}, issn = {}, year = {2008}, pages = {65-68}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2008.12}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - IEEE Computer Architecture Letters TI - DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals IS - 2 SN - SP65 EP68 EPD - 65-68 A1 - Amit Golander, A1 - Shlomo Weiss, A1 - Ronny Ronen, PY - 2008 KW - Multi-core/single-chip multiprocessors KW - Redundant design VL - 7 JA - IEEE Computer Architecture Letters ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2008.12
DMR (Dual Modular Redundancy) was suggested for increasing reliability. Classical DMR consists of pairs of cores that check each other and are pre-connected during manufacturing by dedicated links. In this paper we introduce the Dynamic Dual Modular Redundancy (DDMR) architecture. DDMR supports run-time scheduling of redundant threads, which has significant benefits relative to static binding. To allow dynamic pairing, DDMR replaces the special links with a novel ring architecture. DDMR uses short instruction sequences for validation, smaller than the processor reorder buffer. Such short sequences reduce latencies in parallel programs and save resources needed to buffer uncommitted data. DDMR scales with the number of cores and may be used in large multicore architectures.
Index Terms:
Multi-core/single-chip multiprocessors, Redundant design
Citation:
Amit Golander, Shlomo Weiss, Ronny Ronen, "DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals," IEEE Computer Architecture Letters, vol. 7, no. 2, pp. 65-68, July-Dec. 2008, doi:10.1109/L-CA.2008.12
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