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Proactive Use of Shared L3 Caches to Enhance Cache Communications in Multi-Core Processors
July-December 2008 (vol. 7 no. 2)
pp. 57-60
Sevin Fide, University of California, Irvine
Stephen Jenks, University of California, Irvine
The software and hardware techniques to exploit the potential of multi-core processors are falling behind, even though the number of cores and cache levels per chip is increasing rapidly. There is no explicit communications support available, and hence inter-core communications depend on cache coherence protocols, resulting in demand-based cache line transfers with their inherent latency and overhead. In this paper, we present Software Controlled Eviction (SCE) to improve the performance of multithreaded applications running on multi-core processors by moving shared data to shared cache levels before it is demanded from remote private caches. Simulation results show that SCE offers significant performance improvement (8-28%) and reduces L3 cache misses by 88-98%.
Index Terms:
Multi-core/single-chip multiprocessors, Support for multi-threaded execution
Citation:
Sevin Fide, Stephen Jenks, "Proactive Use of Shared L3 Caches to Enhance Cache Communications in Multi-Core Processors," IEEE Computer Architecture Letters, vol. 7, no. 2, pp. 57-60, July-Dec. 2008, doi:10.1109/L-CA.2008.10
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