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Transaction-Aware Network-on-Chip Resource Reservation
July-December 2008 (vol. 7 no. 2)
pp. 53-56
Zheng Li, Tsinghua University, Beijing
Changyun Zhu, Queen's University, Kingston
Li Shang, University of Colorado at Boulder, Boulder
Robert Dick, Northwestern University, Evanston
Yihe Sun, Tsinghua University, Beijing
Performance and scalability are critically-important for on-chip interconnect in many-core chip-multiprocessor systems. Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication backplane in the many-core era, offers high throughput and excellent scalability. However, these benefits come at the price of router latency due to run-time multi-hop data buffering and resource arbitration. The network accounts for a majority of on-chip data transaction latency. In this work, we propose dynamic in-network resource reservation techniques to optimize run-time on-chip data transactions. This idea is motivated by the need to preserve existing abstraction and general-purpose network performance while optimizing for frequently-occurring network events such as data transactions. Experimental studies using multithreaded benchmarks demonstrate that the proposed techniques can reduce on-chip data access latency by 28.4% on average in a 16-node system and 29.2% on average in a 36-node system.
Index Terms:
On-chip interconnection networks, Interconnections (Subsystems), Interconnection architectures, Parallel Architectures
Citation:
Zheng Li, Changyun Zhu, Li Shang, Robert Dick, Yihe Sun, "Transaction-Aware Network-on-Chip Resource Reservation," IEEE Computer Architecture Letters, vol. 7, no. 2, pp. 53-56, July-Dec. 2008, doi:10.1109/L-CA.2008.9
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