Issue No.02 - July-December (2008 vol.7)
Jaehwan Lee , IUPUI, Indianapolis
Xiang Xiao , IUPUI, Indianapolis
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2008.4
This article proposes a novel parallel, hardware-oriented deadlock detection algorithm for multiprocessor system-on-chips. The proposed algorithm takes full advantage of hardware parallelism in computation and maintains information needed by deadlock detection through classifying all resource allocation events and performing class specific operations, which together make the overall run-time complexity of the new method O(1). We implement the proposed algorithm in Verilog HDL and demonstrate in the simulation that each algorithm invocation takes at most four clock cycles in hardware.
Deadlocks, Algorithms implemented in hardware, Real-time and embedded systems
Jaehwan Lee, Xiang Xiao, "A Parallel Deadlock Detection Algorithm with O(1) Overall Run-time Complexity", IEEE Computer Architecture Letters, vol.7, no. 2, pp. 45-48, July-December 2008, doi:10.1109/L-CA.2008.4