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Hierarchical Instruction Register Organization
July-December 2008 (vol. 7 no. 2)
pp. 41-44
David Black-Schaffer, Stanford University, Stanford
James Balfour, Stanford University, Stanford
William Dally, Stanford University, Stanford
Vishal Parikh, Stanford University, Stanford
JongSoo Park, Stanford University, Stanford
This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and examines the benefits from 1) removing the tag overhead, 2) distributing the storage, 3) adding indirection, 4) adding efficient NOP generation, and 5) sharing instruction memory. The result is a hierarchical instruction register organization that provides a 56% energy and 40% area savings over an already efficient Filter Cache.
Index Terms:
Low-power design, Instruction fetch, RISC/CISC, VLIW architectures
Citation:
David Black-Schaffer, James Balfour, William Dally, Vishal Parikh, JongSoo Park, "Hierarchical Instruction Register Organization," IEEE Computer Architecture Letters, vol. 7, no. 2, pp. 41-44, July-Dec. 2008, doi:10.1109/L-CA.2008.7
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