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Issue No.01 - January-June (2008 vol.7)
pp: 1
A. Biswas , Intel Corp., Hudson, MA
P. Racunas , Intel Corp., Hudson, MA
J. Emer , Intel Corp., Hudson, MA
S.S. Mukherjee , Intel Corp., Hudson, MA
ACE (architecturally correct execution) analysis computes AVFs (architectural vulnerability factors) of hardware structures. AVF expresses the fraction of radiation-induced transient faults that result in user-visible errors. Architects usually perform this analysis on a high-level performance model to quickly compute per-structure AVFs. If, however, low-level details of a microarchitecture are not modeled appropriately, then their effects may not be reflected in the per-structure AVFs. In this paper we refute Wang, et al.'s (2007) claim that this detail is difficult to model and imposes a practical threshold on ACE analysis that forces its estimates to have a high error margin. We show that carefully choosing a small amount of additional detail can result in a much tighter AVF bound than Wang, et al. were able to achieve in their refined ACE analysis. Even the inclusion of small details, such as read/write pointers and appropriate inter-structure dependencies, can increase the accuracy of the AVF computation by 40% or more. We argue that this is no different than modeling the IPC (instructions per cycle) of a microprocessor pipeline. A less detailed performance model will provide less accurate IPCs. AVFs are no different.
Performance analysis, Hardware, Microarchitecture, High performance computing, Microprocessors, Pipelines, Computational modeling, Protection, Target tracking,Testing and Fault-Tolerance, Performance and Reliability, Reliability
A. Biswas, P. Racunas, J. Emer, S.S. Mukherjee, "Computing Accurate AVFs using ACE Analysis on Performance Models: A Rebuttal", IEEE Computer Architecture Letters, vol.7, no. 1, pp. 1, January-June 2008, doi:10.1109/L-CA.2007.19
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