Issue No.01 - January-June (2008 vol.7)
A. Roth , Dept. of Comput. & Inf. Sci., Univ. of Pennsylvania, Philadelphia, PA
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.15
Several proposed techniques including CPR (checkpoint processing and recovery) and NoSQ (no store queue) rely on reference counting to manage physical registers. However, the register reference counting mechanism itself has received surprisingly little attention. This paper fills this gap by describing potential register reference counting schemes for NoSQ, CPR, and a hypothetical NoSQ/CPR hybrid. Although previously described in terms of binary counters, we find that reference counts are actually more naturally represented as matrices. Binary representations can be used as an optimization in specific situations.
Registers, Counting circuits, Physics computing, Information science, Proposals, Microarchitecture, Engines,dynamically-scheduled and statically-scheduled implementation, Micro-architecture implementation considerations, Superscalar
A. Roth, "Physical register reference counting", IEEE Computer Architecture Letters, vol.7, no. 1, pp. 1, January-June 2008, doi:10.1109/L-CA.2007.15