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A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip
July-December 2007 (vol. 6 no. 2)
pp. 41-44
| ASCII Text | x | ||
| Xiang Xiao, Jaehwan Lee, "A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip," IEEE Computer Architecture Letters, vol. 6, no. 2, pp. 41-44, July-December, 2007. | |||
| BibTex | x | ||
| @article{ 10.1109/L-CA.2007.11, author = {Xiang Xiao and Jaehwan Lee}, title = {A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip}, journal ={IEEE Computer Architecture Letters}, volume = {6}, number = {2}, issn = {1556-6056}, year = {2007}, pages = {41-44}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.11}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - IEEE Computer Architecture Letters TI - A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip IS - 2 SN - 1556-6056 SP41 EP44 EPD - 41-44 A1 - Xiang Xiao, A1 - Jaehwan Lee, PY - 2007 KW - Deadlocks KW - Algorithms implemented in hardware KW - Real-time and embedded systems VL - 6 JA - IEEE Computer Architecture Letters ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.11
Given the projected dramatic increase in the number of processors and resources in a system-on-a-chip, a quadratic increase in the likelihood of deadlock is predicted due to complex system behavior. To deal with this issue, we here present a novel parallel hardware-oriented deadlock detection algorithm with O(1) deadlock detection and O(min(m,n)) preparation, where m and n are the numbers of processes and resources, respectively. Our contributions are (i) the first O(1) deadlock detection hardware implementation and (ii) a new algorithmic method of achieving O(min(m,n)) overall run-time complexity. We implement our algorithm in Verilog HDL and demonstrate that deadlock detection always takes only two clock cycles regardless of the size of a system (i.e., m and n).
Index Terms:
Deadlocks, Algorithms implemented in hardware, Real-time and embedded systems
Citation:
Xiang Xiao, Jaehwan Lee, "A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip," IEEE Computer Architecture Letters, vol. 6, no. 2, pp. 41-44, July-Dec. 2007, doi:10.1109/L-CA.2007.11
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