Issue No.02 - July-December (2007 vol.6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.11
Given the projected dramatic increase in the number of processors and resources in a system-on-a-chip, a quadratic increase in the likelihood of deadlock is predicted due to complex system behavior. To deal with this issue, we here present a novel parallel hardware-oriented deadlock detection algorithm with O(1) deadlock detection and O(min(m,n)) preparation, where m and n are the numbers of processes and resources, respectively. Our contributions are (i) the first O(1) deadlock detection hardware implementation and (ii) a new algorithmic method of achieving O(min(m,n)) overall run-time complexity. We implement our algorithm in Verilog HDL and demonstrate that deadlock detection always takes only two clock cycles regardless of the size of a system (i.e., m and n).
Deadlocks, Algorithms implemented in hardware, Real-time and embedded systems
Xiang Xiao, "A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip", IEEE Computer Architecture Letters, vol.6, no. 2, pp. 41-44, July-December 2007, doi:10.1109/L-CA.2007.11