Issue No.02 - July-December (2007 vol.6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.10
With the trend towards increasing number of cores in a multicore processors, the on-chip network that connects the cores needs to scale efficiently. In this work, we propose the use of high-radix networks in on-chip networks and describe how the flattened butterfly topology can be mapped to on-chip networks. By using high-radix routers to reduce the diameter of the network, the flattened butterfly offers lower latency and energy consumption than conventional on-chip topologies. In addition, by properly using bypass channels in the flattened butterfly network, non-minimal routing can be employed without increasing latency or the energy consumption.
on-chip networks, topology, flattened butterfly, high-radix routers
John Kim, James Balfour, William J. Dally, "Flattened Butterfly Topology for On-Chip Networks", IEEE Computer Architecture Letters, vol.6, no. 2, pp. 37-40, July-December 2007, doi:10.1109/L-CA.2007.10