Issue No.02 - July-December (2007 vol.6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.9
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed memory hierarchy enhancements for coherence traffic reduction and prefetching suggest that additional useful patterns emerge with a macroscopic, coarse-grain view. This paper presents RegionTracker, a dual-grain, on-chip cache design that exposes coarse-grain behavior while maintaining block-level communication. RegionTracker eliminates the extraneous, often imprecise coarse-grain tracking structures of previous proposals. It can be used as the building block for coarse-grain optimizations, reducing their overall cost and easing their adoption. Using full-system simulation of a quad-core chip multiprocessor and commercial workloads, we demonstrate that RegionTracker overcomes the inefficiencies of previous coarse-grain cache designs. We also demonstrate how RegionTracker boosts the benefits and reduces the cost of a previously proposed snoop reduction technique.
Jason Zebchuk, Andreas Moshovos, "A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy", IEEE Computer Architecture Letters, vol.6, no. 2, pp. 33-36, July-December 2007, doi:10.1109/L-CA.2007.9