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| José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt, "Dynamic Predication of Indirect Jumps," IEEE Computer Architecture Letters, vol. 6, no. 2, pp. 25-28, July-December, 2007. | |||
| BibTex | x | ||
| @article{ 10.1109/L-CA.2007.7, author = {José A. Joao and Onur Mutlu and Hyesoon Kim and Yale N. Patt}, title = {Dynamic Predication of Indirect Jumps}, journal ={IEEE Computer Architecture Letters}, volume = {6}, number = {2}, issn = {1556-6056}, year = {2007}, pages = {25-28}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.7}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - IEEE Computer Architecture Letters TI - Dynamic Predication of Indirect Jumps IS - 2 SN - 1556-6056 SP25 EP28 EPD - 25-28 A1 - José A. Joao, A1 - Onur Mutlu, A1 - Hyesoon Kim, A1 - Yale N. Patt, PY - 2007 KW - Processor Architectures KW - Computer Systems Organization KW - Pipeline processors KW - Single Data Stream Architectures KW - Instruction fetch KW - Micro-architecture implementation considerations KW - Superscalar KW - dynamically-scheduled KW - and statically-scheduled implementation KW - Micro-architecture implementation considerations VL - 6 JA - IEEE Computer Architecture Letters ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.7
Indirect jumps are used to implement increasingly common programming language constructs such as virtual function calls, switch-case statements, jump tables, and interface calls. Unfortunately, the prediction accuracy of indirect jumps has remained low because many indirect jumps have multiple targets that are difficult to predict even with specialized hardware. This paper proposes a new way of handling hard-to-predict indirect jumps: dynamically predicating them. The compiler identifies indirect jumps that are suitable for predication along with their control-flow merge (CFM) points. The microarchitecture predicates the instructions between different targets of the jump and its CFM point if the jump turns out to be hardto-predict at run time. We describe the new indirect jump predication architecture, provide code examples showing why it could reduce the performance impact of jumps, derive an analytical cost-benefit model for deciding which jumps and targets to predicate, and present preliminary evaluation results.
Index Terms:
Processor Architectures, Computer Systems Organization, Pipeline processors, Single Data Stream Architectures, Instruction fetch, Micro-architecture implementation considerations, Superscalar, dynamically-scheduled, and statically-scheduled implementation, Micro-architecture implementation considerations
Citation:
José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt, "Dynamic Predication of Indirect Jumps," IEEE Computer Architecture Letters, vol. 6, no. 2, pp. 25-28, July-Dec. 2007, doi:10.1109/L-CA.2007.7
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