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Nahalal: Cache Organization for Chip Multiprocessors
January-June 2007 (vol. 6 no. 1)
pp. 21-24
| ASCII Text | x | ||
| Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri Weiser, "Nahalal: Cache Organization for Chip Multiprocessors," IEEE Computer Architecture Letters, vol. 6, no. 1, pp. 21-24, January-June, 2007. | |||
| BibTex | x | ||
| @article{ 10.1109/L-CA.2007.6, author = {Zvika Guz and Idit Keidar and Avinoam Kolodny and Uri Weiser}, title = {Nahalal: Cache Organization for Chip Multiprocessors}, journal ={IEEE Computer Architecture Letters}, volume = {6}, number = {1}, issn = {1556-6056}, year = {2007}, pages = {21-24}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.6}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - IEEE Computer Architecture Letters TI - Nahalal: Cache Organization for Chip Multiprocessors IS - 1 SN - 1556-6056 SP21 EP24 EPD - 21-24 A1 - Zvika Guz, A1 - Idit Keidar, A1 - Avinoam Kolodny, A1 - Uri Weiser, PY - 2007 KW - Cache memories KW - Design Styles KW - Memory Structures KW - Hardware KW - Multi-core/single-chip multiprocessors KW - Parallel Architectures KW - Processor Architectures KW - Computer Systems Organization VL - 6 JA - IEEE Computer Architecture Letters ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.6
This paper addresses cache organization in Chip Multiprocessors (CMPs). We show that in CMP systems it is valuable to distinguish between shared data, which is accessed by multiple cores, and private data accessed by a single core. We introduce Nahalal, an architecture whose novel floorplan topology partitions cached data according to its usage (shared versus private data), and thus enables fast access to shared data for all processors while preserving the vicinity of private data to each processor. Nahalal exhibits significant improvements in cache access latency compared to a traditional cache design.
Index Terms:
Cache memories, Design Styles, Memory Structures, Hardware, Multi-core/single-chip multiprocessors, Parallel Architectures, Processor Architectures, Computer Systems Organization
Citation:
Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri Weiser, "Nahalal: Cache Organization for Chip Multiprocessors," IEEE Computer Architecture Letters, vol. 6, no. 1, pp. 21-24, Jan.-June 2007, doi:10.1109/L-CA.2007.6
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