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Nahalal: Cache Organization for Chip Multiprocessors
January-June 2007 (vol. 6 no. 1)
pp. 21-24
This paper addresses cache organization in Chip Multiprocessors (CMPs). We show that in CMP systems it is valuable to distinguish between shared data, which is accessed by multiple cores, and private data accessed by a single core. We introduce Nahalal, an architecture whose novel floorplan topology partitions cached data according to its usage (shared versus private data), and thus enables fast access to shared data for all processors while preserving the vicinity of private data to each processor. Nahalal exhibits significant improvements in cache access latency compared to a traditional cache design.
Index Terms:
Cache memories, Design Styles, Memory Structures, Hardware, Multi-core/single-chip multiprocessors, Parallel Architectures, Processor Architectures, Computer Systems Organization
Citation:
Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri Weiser, "Nahalal: Cache Organization for Chip Multiprocessors," IEEE Computer Architecture Letters, vol. 6, no. 1, pp. 21-24, Jan.-June 2007, doi:10.1109/L-CA.2007.6
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