Issue No.01 - January-June (2007 vol.6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2007.3
Cache Partitioning has been proposed as an interesting alternative to traditional eviction policies of shared cache levels in modern CMP architectures: throughput is improved at the expense of a reasonable cost. However, these new policies present different behaviors depending on the applications that are running in the architecture. In this paper, we introduce some metrics that characterize applications and allow us to give a clear and simple model to explain final throughput speed ups.
Performance Analysis and Design Aids, Memory Structures, Hardware, Cache memories, Design Styles, Memory Structures, Hardware, Multi-core/single-chip multiprocessors, Parallel Architectures, Processor Architectures, Computer Systems Organization, Memory hierarchy, Micro-architecture implementation considerations, Processor Architectures, Computer Systems Organization, Modeling techniques, Performance of Systems, Computer Systems Organization
Francisco Cazorla, Alex Ramirez, Mateo Valero, "Explaining Dynamic Cache Partitioning Speed Ups", IEEE Computer Architecture Letters, vol.6, no. 1, pp. 1-4, January-June 2007, doi:10.1109/L-CA.2007.3