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Issue No.01 - January-June (2007 vol.6)
pp: 5-8
ABSTRACT
Circuit-switched networks can significantly lower the communication latency between processor cores, when compared to packet-switched networks, since once circuits are set up, communication latency approaches pure interconnect delay. However, if circuits are not frequently reused, the long set up time and poorer interconnect utilization can hurt overall performance. To combat this problem, we propose a hybrid router design which intermingles packet-switched flits with circuit-switched flits. Additionally, we co-design a prediction-based coherence protocol that leverages the existence of circuits to optimize pair-wise sharing between cores. The protocol allows pair-wise sharers to communicate directly with each other via circuits and drives up circuit reuse. Circuit-switched coherence provides overall system performance improvements of up to 17% with an average improvement of 10% and reduces network latency by up to 30%.
INDEX TERMS
On-chip interconnection networks; Parallel Architectures; Processor Architectures; Computer Systems Organization, Multi-core/single-chip multiprocessors; Parallel Architectures; Processor Architectures; Computer Systems Organization, Memory hierarchy; Micro-architecture implementation considerations; Processor Architectures; Computer Systems Organization
CITATION
Natalie Enright Jerger, Mikko Lipasti, Li-Shiuan Peh, "Circuit-Switched Coherence", IEEE Computer Architecture Letters, vol.6, no. 1, pp. 5-8, January-June 2007, doi:10.1109/L-CA.2007.2
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