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Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy
January-June 2007 (vol. 6 no. 1)
pp. 13-16
Some processors designed for consumer applications, such as Graphics Processing Units (GPUs) and the CELL processor, promise outstanding floating-point performance for scientific applications at commodity prices. However, IEEE single precision is the most precise floating-point data type these processors directly support in hardware. Pairs of native floatingpoint numbers can be used to represent a base result and a residual term to increase accuracy, but the resulting order of magnitude slowdown dramatically reduces the price/performance advantage of these systems. By adding a few simple microarchitectural features, acceptable accuracy can be obtained with relatively little performance penalty. To reduce the cost of native-pair arithmetic, a residual register is used to hold information that would normally have been discarded after each floating-point computation. The residual register dramatically simplifies the code, providing both lower latency and better instruction-level parallelism.
Index Terms:
Cost/performance, High-Speed Arithmetic, Arithmetic and Logic Structures, Hardware, Hardware/software interfaces, General, Computer Systems Organization, Micro-architecture implementation considerations, Processor Architectures, Computer Systems Organization, Multiple precision arithmetic, General, Numerical Analysis, Mathematics of Computing, Graphics processors, Hardware Architecture, Computer Graphics, Computing Methodologies
Citation:
William R. Dieter, Akil Kaveti, Henry G. Dietz, "Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy," IEEE Computer Architecture Letters, vol. 6, no. 1, pp. 13-16, Jan.-June 2007, doi:10.1109/L-CA.2007.1
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