Issue No.01 - January-June (2006 vol.5)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/L-CA.2006.7
Hardware predictor designers have incorporated hysteresis and/or bias to achieve desired behavior by increasing the number of bits per counter. Some resulting proposed predictor designs are currently impractical because their counter tables are too large. We describe a method for dramatically reducing the amount of storage required for a predictor?s counter table with minimal impact on prediction accuracy. Probabilistic updates to counter state are implemented using a hardware pseudo-random number generator to increment or decrement counters a fraction of the time, meaning fewer counter bits are required. We demonstrate the effectiveness of probabilistic updates in the context of Fields et al.?s critical path predictor, which employsa biased 6-bit counter. Averaged across the SPEC CINT2000 benchmarks, our 2-bit and 3-bit probabilistic counters closely approximate a 6-bit deterministic one (achieving speedups of 7.75% and 7.91% compared to 7.94%) when used for criticality based scheduling in a clustered machine. Performance degrades gracefully, enabling even a 1-bit probabilisitic counter to outperform the best 3-bit deterministic counter we found.
Nicholas Riley, "Probabilistic Counter Updates for Predictor Hysteresis and Bias", IEEE Computer Architecture Letters, vol.5, no. 1, pp. 18-21, January-June 2006, doi:10.1109/L-CA.2006.7