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Computer Architecture Letters
2006
Issue No. 1 - January-June
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IEEE Computer Architecture Letters
January-June 2006 (vol. 5 no. 1)
ISSN: 1556-6056
Table of Contents
Papers
Balanced Instruction Cache: Reducing Conflict Misses of Direct-Mapped Caches through Balanced Subarray Accesses
(Abstract)
Chuanjun Zhang
ABSTRACT
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From Sequential Programs to Concurrent Threads
(Abstract)
Guilherme Ottoni
Ram Rangan
Adam Stoler
Matthew J. Bridges
David I. August
ABSTRACT
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Topology Optimization of Interconnection Networks
(Abstract)
Amit K. Gupta
William J. Dally
ABSTRACT
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Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors
(Abstract)
Tomer Y. Morad
Uri C. Weiser
Avinoam Kolodny
Mateo Valero
Eduard Ayguad?
ABSTRACT
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Probabilistic Counter Updates for Predictor Hysteresis and Bias
(Abstract)
Nicholas Riley
Craig Zilles
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A Case for Fault Tolerance and Performance Enhancement Using Chip Multi-Processors
(Abstract)
Huiyang Zhou
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Adopting System Call Based Address Translation into User-Level Communication
(Abstract)
Moon-Sang Lee
Sang-Kwon Lee
Joonwon Lee
Seung-Ryoul Maeng
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Data Parallel Address Architecture
(Abstract)
Jung Ho Ahn
William J. Dally
ABSTRACT
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In-Network Cache Coherence
(Abstract)
Noel Eisley
Li-Shiuan Peh
Li Shang
ABSTRACT
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Performance Modeling Using Monte Carlo Simulation
(Abstract)
Ram Srinivasan
Jeanine Cook
Olaf Lubeck
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Foreword
(PDF)
Jean-Luc Gaudiot
Yale Patt
Kevin Skadon
ABSTRACT
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